The transistor symbol

Together with Maple Martin I browsed through our group’s library and came across a couple of books by Prof. Kjell Jeppsson (from Chalmers University of Technology). One of the books, “Praktisk transistorteknik” (1965), triggered me – of course. Browsing through the pages, I realize that the transistor symbol he used in his figures looked unfamiliar to me. It was the 1965 version of the Swedish standard symbol for the junction transistor.

Where does the symbol come from? My short-story/interpretation.

So, in case you might be taking the course in analog electronics at the moment: this post aligns quite well with the topic we are currently reading. Take a quick glance at my impressionistic skills below. I have depicted the first point-contact transistor (to the left) and the “first” junction transistor (to the right). It is pretty obvious from where the – today, widely used – bipolar symbol comes. The symbol is found at the bottom left of the picture. Above that my redrawing of the famous Bell Labs photo. The v-shaped piece of plastic, on which the phosphor-bronze traces where applied, guides the emitter and collector to and from the germanium plate which is attached to the metal frame which the base in turn is connected to. The “housing” around the transistor is modeled by a circle around the lines.

To the right in the picture, we see a sketch of the junction transistor. A more homogeneous solution. From left to right we have the emitter, base, and collector. Here the currents go “through” the semiconductor whereas in the point contact transistor it goes on the surface (well, arguably, but true to a first degree …). Looking at the international symbol, it does not really make sense – if one has time to care about those kind of things. The Swedish standard institute (SSI) symbol, from 1965, is depicted below the junction transistor. It turns out to be a bit more of logic behind that one. The base “cuts” the emitter and collector and the current goes straight through the base. However, the symbol lost the battle.

Transistor symbols

Transistor symbols

I guess the thing was that the junction transistor was invented and patented quite soon after the delivery of the 1947 Christmas present in the shape of a point-contact transistor at Bell labs. Due to the more integrated nature of the junction transistor it was also a better choice for most users. In addition, the junction transistor has much higher gain (200 vs 20), was less noisy, and could take on higher power levels. (Not as high as for tubes which were even faster. In fact the point-contact transistor initially had a higher gain-bandwidth product.). Due to this rapid development, the old symbol made it into the books. There was no point in developing a new one (unless it was exported to another continent).


This post is not supposed to be very comprehensive when comparing the MOS with the BIP (bipolar) transistor. However, I thought it could be nice to have it outlined on a single sheet here. MOS stands for metal oxide semiconductor.

Inte picture below we find Lilienfeld vs Shockley. (Yes, yes, yes, one can argue about who did what, etc., but I will let them represent the two transistors). Lilienfeld represents a more square symbol and a “simpler” expression of the current as function of input voltage (in its desired operating region): a polynomial – the square of the input voltage, ube. Shockley presents an exponential function instead – the diode equation. I have sketched the currents as functions of the input voltage and we see that even though the square (MOS) is stronger in the beginning, the exponential quickly comes up to pace and produces higher currents.

The MOS layout is more compact compared to the bipolar. The MOS offers an infinite input resistance (well). The bipolar does not. In fact it must have an input current to operate as desired.

Considering the small signal schematics, the parameters gm (transconductance), gds/go (output conductance) and gp (input conductance) can all be derived as dependent on the current through the transistor. The higher current, the higher everything, sort of. Arguably, this implies that the gain is more or less with current.
At the bottom of the figure, we find the intrinsic gain of the transistors.

For the MOS it is the Early voltage over the effektive input voltage, i.e., gate-source voltage minus the threshold voltage. For the bipolar it is the Early voltage over the thermal voltage (~26 mV). These two gain expressions actually tell us that it is quite likely that the gain is higher for the bipolar than the MOS! (This can also be seen from the MOS transistor operating in the subthreshold region).

Why larger? It is hard to push down the MOS effective voltage to the required 52 mV to match the bipolar relying on the thermal voltage.


Developing labs

We are facing quite a lot of challenges within the field of electronics at our university. In short: there are fewer and fewer students taking electronics courses and we should adapt to that situation.

There would be at least two ways to address the problem: either we scale down or we make the courses more interesting such that, in the end, more students will choose to study electronics. The “problem” however, might be that we are a bit late to offer this change at the university level. Most likely we have to be much more active and visible for children/pupils already in their early teens.

Anyways, while changing courses, why not study one of the perhaps most important elements of the course: the laboratory. This is in some sense the only occasion when the students can practice and try the theory in a context. That sounds easy – doesn’t it? Take a course in basic electrical circuits: It might contain course elements such as DC (Ohm’s law, KCL, KVL) and AC currents (jw, power), as well as something around frequency analysis (amplitude characteristics). Three main parts of the course. Easy as a pie: introduce three laboratories – one on each subject. Happy days. End of story. … Or?

A while ago I visited a seminar hosted by Anna-Karin Carstensen at the Norrköping Campus. A while ago they were intensly studying how the learning process takes place in the laboratory series. They monitored students, filmed them during the laboratory work (asking for permissions of course). Then they analyzed the results. It was for them then quite visible where there were flaws in the laboratories, regardless if theory had been taught in lectures or not. It did not matter if the lecturer thought that all material were there, at the students’ hands. There were simply not the required processes enabling the students to form the links connecting chunks of knowledge/wisdom to to move on in the laboratory series and grasp the knowledge.

It was part of Carstensens Ph.D. studies to monitor these laboratories and develop a method to create a new laboratory where students should more easily link between pieces of knowledge to understand the “whole” picture.

Yes, I know that nomenclature fails me, I am not trained in this field of research. I am trying to give my review in a straight-forward approach.

Consider the picture below, which at a first glance might look a bit simple. It depicts the learning processes, the links, in a laboratory, where the aim is to sort of “understand the Laplace transform”. How do you make the connection between time domain, frequency domain, poles and zeros, and the Laplace transform. The task of the lab is to curve-fit and find important parameters of the step response of an RLC circuit (resistor, inductor, capacitor). By doing this, a better understanding for how the location of poles and zeros, i.e., coefficients in the Laplace polynomial, affect the step response, should be developed.

This picture is from Carstensen’s dissertation and I have got the permission to publish it here..

Now, the point is to sit down and actually look at the laboratory and its manual. What pieces of the puzzle do we have at hand? How will the students see these pieces? You want the students to bridge all links (verbs btw, actions), such that they move around freely and “understand”, “conceive”, in the graph above.

Let us start in the top left corner of the circle (you know what I mean…). Students are given a real circuit, including a schematic (at this stage of their training, they conceive the schematic as a “real circuit”). From that you derive the differential equation. From there on, through replacing operators with s or 1/s, you get to Mr. Laplace. Or you would get to Laplace from the real circuit by doing some KCL&KVL exercises and replacing C with 1/sC, etc. Through tables you would get from Laplace to the time-domain representation, you would be plotting it and you would be comparing it with the measured graph. The graph is measured on our real circuit. And we are back at stage one. That sounds pretty straight-forward right?

Well, yes, perhaps. But actually, you want the student to understand, not just walk around the circle and applying a standard set of rules. You want them to do the connections and not a) get stuck in smaller loops and not b) run the outer loop. They must be able to get from any point to any other. Those links, or enablers for them, must be in the lab too, otherwise it is just a fill-in-the-blank-boxes exercise.

Much more can be said, I just wanted to inspire to do some more reading at before you plan your next lab and I will try to adapt this way of thinking for next year’s TSTE92 Electrical Circuits.

Another bound on power consumption in DACs

I wanted to go back to the previous post where we investigated the trade-offs between speed, resolution and power consumption in a digital-to-analog converter (DAC). That gave us a bound in that triangle.

What if we use another starting point in our argument rather than noise?

Same type of DAC

Consider the DAC in the figure. Same type of DAC as last time. We have a current through a resistor forming the voltage. What is the minimum possible quanta through the resistor? Leading question … Assume the least significant bit is determined by one single electron during the sampling period.
The average current for a single electron is given by

I = q_0 / \Delta T = q_0 \cdot f_s

where f_s is the sample frequency and q_0 = 0.1602 aC is the elementary charge of the electron. (Let us ignore quantum effects and those things. Let us be traditional and assume we know where the electron is, before we open the box with the cat, …)

Small value?

So, is this a small or a large value?
Well, assume a resistive load of R_L. The (average) voltage for that particular charge, corresponding to one least significant bit, would be

\Delta V = R_L \cdot I = R_L \cdot q_0 \cdot f_s

Assume 100 Ohms in the load, and a sample frequency of 600 MHz. We get

\Delta V = 100 \cdot 0.1602 \cdot 10^{-18} \cdot 600 \cdot 10^6 = 10^{-8}

which is 10 nV. This would correspond to something like:

  • In a 16-bit converter, this would mean that the peak voltage is some 655 uV.
  • In a 20-bit converter, sampled at 1.2 GHz, the peak voltage is some 21 mV.

The voltages can simply not be less than that for the given sample frequencies and resolutions. Otherwise we have to split the electron (buying Swedes a cake).

I think it is actuall rather interesting: the faster you sample, the less electrons will be there for each least significant bit (LSB).

Full-swing signal

With a full-scale sinusoid signal in place, we can find the average power as

P = V_{ref}^2 / R_L/8 = 2^{2 N - 3} \cdot \frac{q_0^2}{T^2} R_L = R_L \cdot 2^{2 N - 3} \cdot q_0^2 \cdot f_s^2

which is then the absolute minimum possible power that must be consumed to obtain a certain resolution.

Are we having fun yet?

Just for the fun of it, let us rewrite the formula a bit

P = C_L R_L \cdot 2^{2 N - 3} \cdot \frac{q_0 }{kT} \cdot \frac{kT} {C_L} \cdot q_0 \cdot f_s^2 = 2^{2 N - 3} \cdot \frac{q_0 }{kT} \cdot \frac{kT} {C_L} \cdot q_0 \cdot f_s / \pi

where we have assumed that we also have to guarantee the bandwidth, not just the sample frequency and voltage levels.
In the equation, we can identify the 26-mV term (q/kT), a noise power kT/C, and some constants. Possibly, it could be related to the previous post. Philosophically (?) one could also think what the thermal noise looks like when we push single electrons back and forth.


How fast do we need to sample over a 100-Ohm load to get a 1-V drop with a single electron? (Once again, from a mathematical point of view, and possibly not the correct physical description of the scenario).

V = R_L \cdot I = R_L \cdot q_0 \cdot f_s = 1

f_s = 1 / (R_L \cdot q_0) = 62 \cdot 10^{15}

Ok, so 60 PHz is rather fast… if we would correlate with light, it would end up in the UV domain, 100 times less than visible light. And now we kind of entering the photoelectric effects, sort of …

Why doesn’t the gain change in my CMOS common-source amplifier?


The other day I provided the students in my course: “TSTE08 Analog and discrete-time integrated circuits” a quiz. Perhaps it was a bit of a cryptical one, but I wanted to point out some of the difficulties with the current-voltage relationship in an analog amplifier, and the complexities in the choice of electrical vs. physical design parameters.

So, with this post I hope to give you both an insight in that quiz, but also an insight in a clever (?) way to set the DC operating points in your circuit…

The quiz

The quiz related to the common-source amplifier. The input is typically connected to the NMOS and a PMOS forms as active load. Moreover:

Assume I have a common-source amplifier with an active load. Further assume that the output and input DC voltages are fixed.
What should I do to increase the DC gain of my amplifier? Use hand-calculation formulas.

1) Increase the current through the amplifier
X) Increase the width of the transistors
2) Increase the length of the transitors

Any combination of those three could be correct.

So, perhaps the quiz it was a bit cryptical, yes.


First suggestion on how to attack the problem: find the desired relations you need. For example, the gain, A_0 is something like:

A_0 = \frac{g_{mn}}{g_{out}} = \frac{g_{mn}}{g_{p}+g_n} = \frac{\frac{2 I_D }{V_{EFF}}{}}{\lambda_p I_D + \lambda_n I_D} = \frac{1}{\frac{\lambda_p + \lambda_n}{2} \cdot V_{EFF}} = \frac{1}{\lambda \cdot V_{EFF}}

where we can clearly see that it is “independent” (!) on the current through the amplifier. The

V_{EFF} = V_{GS} - V_{Tn} = V_{i n} - V_{Tn}

is the effective input (DC) overdrive voltage (which we cannot touch as per the quiz!). We also know from “hand calculations” that

I_D = \alpha \cdot V_{EFF}^2

and since V_{EFF} cannot change we also see that I_D / \alpha obviously has to be constant.
Technically, we could increase both current and size such that the ratio is kept constant. However, it still does not help if we look at the gain expression above. The gain is independent on the ratio, if the effective voltage remains constant.
Options 1 and X are no valid options.

So, what about transistor lengths?

Also here we need to look at another common relation for a MOS transistor: we know that with longer widths, the channel length modulation reduces, so we get:

\lambda \propto 1 / L

such that

A_0 \propto \frac{L}{ V_{EFF}}

the channel length pops up in the numerator.

This means answer 2 is correct.
By increasing the channel length of the transistors, we effectively increase the output impedance and also increase the gain without touching the DC level (hand calculations).

Is that really correct?

Well, is it really correct? Maybe not super-duper correct if we take all second- and third-order effects into account. There are probably small variations to the gain if we change current and width.

Let us hook up a testbench. Below we find a common-source stage with a somewhat cryptical circuit in the box on the top. That is actually a tuned current source that guarantees that the the operating points, input and output DC voltages, are kept constant. The loop with the vcvs (amplifier) will increase the current through the circuit and make the output voltage follow the reference voltage in the top left. If we also make sure that the transistors are sized well to operate in saturation region for the sweeps we will do shortly, we are more or less fine to prove our point.


Then we run a DC input voltage sweep and an AC input sweep. Below we find the frequency response on the left and the DC response on the right. The left-hand figure tells us that the DC gain is somewhere around 25dB-ish. From the right-hand figure, we see that the output DC voltage stays stuck at some 0.6 V.


Varying widths (effectively changing current)

We do a parametric sweep and capture the DC gain value (from the frequency sweep at 10 Hz) and plot it as a function of the transistor width. (Sorry for the thin line here, you might have to press the picture for a more clear view.) We see that the gain increases from some 23.5 to some 24.7 dB when increasing the width 100 (!) times. In a linear scale that is a very small change for such a large variation and practically there is no (significant) change in gain.


Varying lengths

Then we do a parametric sweep and capture the DC gain value, still at 10 Hz from the frequency sweep, and plot it as a function of the transistor length. (Sorry for the thin line here, you might have to press the picture for a more clear view.) The gain now increases 17.5 to 28 dB when increasing channel length 10 (!) times. In a linear scale this is now a very significant change, almost four times (12 dB).


A comment on the test bench

The trick in the test bench is quite useful actually. It is much more convenient than running the circuit in open loop to try to find the absolute settings. If the gain is very high, you have to do quite a few sweeps around the operating point in order for the simulator to have you find the best point.

The trick is also the convenient sp2tswitch that Cadence/spectre provides to simulate a circuit in different conditions. The AC simulation (which is run after DC) will inherit the DC settings and run the AC analysis around those operating points. Notice that I had to connect the two inputs of the vcvs (essentially an differential operational amplifier with a gain of 1000) to the reference voltage during AC to force the gate of the PMOS to be quiet. It is not clear why this was needed.

Can we trust the models?

I am preparing this years version of the analog integrated circuit courses (TSTE08 and TSEI12. For this purpose, I need to tweak some of the model cards for the simulator. We do not need the most fancy processes to demonstrate analog circuit design in the courses.

However, while doing this I revisited one old post:

as a way (thanks, Aamir) to plot e.g. the transconductance and output conductance of e.g. a common-source circuit. That is quite powerful in case you want to demonstrate the importance of choosing your operating region or operating point in general. With the above mentioned post, we can plot the parameters, such as the operating region!, as function of e.g. input voltage, etc.

I’ve got a bit confused by the results first after realizing that I was invoking a level-1 model of the MOS in my testbench. Think Shichman-Hodges, hand calculations, if-statements, etc. There are so much material on the properties of the different models and I do not intend to touch upon them here, instead I serve a small comparison…

Consider the testbench below. It is a common-source stage with an NMOS driving transistor with an active, current-mirror load, where we set the current with an ideal current source, ie., forcing current through the drive transistor. We then want to sweep the input transistor DC voltage to find an operating point of interest (or at least get an idea of the operation).

I will now switch in different models in my model card, and I also append one of those magic extras in an additional file to be able to plot what I want:

save Mdrive:region
save Mdrive:gds
save Mdrive:gm

Level 1

Let us look at the results for different models. First, we start with level 1. One of the most basic models and used for old technologies. We plot the gain (gm/gds), the output voltage (vOut), the transistor’s operating region, the transconductance (gm), and the conductance (gds) as function of the input DC voltage, vInDc.

We can for example see how the transistor sweeps through different operating regions (green, brickwall): cut-off (0) – subthreshold (3) – saturation (2) – linear (1). The transconductance (gm, yellow) follows a more or less linear curve as soon as we enter the saturation region. (Notice that gm = alpha x Veff according to the good-old hand-calculations.

The oddity in this simulation is the gain (blue). Notice that it is plotted in logarithmic scale (!) and for low input DC voltage the gain is huge ~ 30000. We even see that we do have some divide-by-zero happening for low values. Clearly this indicates something unrealistic with the model.


Level 2

Let us see what level 2 can offer. This is the so-called Grove-Frohman model (Google! Interesting guys.) Below we find a similar picture. In this case, the gain looks much more moderate. The treshold voltage is different for this level, which implies a shift of the region towards higher voltages. We see a more soft behavior in the transconductance, but still – at the shift from subthreshold to saturation region (around 0.65 V vInDc) – we see a tendency of a discontinuity. (Notice that we have a finer resolution in vInDc than illustrated by the tick-marks in the graphs).


Level 3

Level 3 – more based on empirical results. Similarly here, we see a discontinuity around the shift from cut-off/subthreshold to the saturation region. Even on the gain curve, we see a clear peaking indicating something strange. It would be more realistic to think of the transition as something continuous. Remember that the blue gain curve is still in a logarithmic scale. The peak hits some 40000 times of gain. The transconductance (yellow) is not all linear as in level 1.


Level 49

Let’s switch to level 49. This is a more modern model and is also called he BSIM3v3 (which comes in different flavours…) Once again the threshold voltage is different. The nice thing here now is that we see a smooth transition between the operating regions – especially from the subthreshold to saturation range. One would think that it is a more accurate model of the real-life transistor, but of course we cannot be all sure.

The gain seems more realistic, no sharp spikes or jumps, and settling towards a final value in a smooth fashion, both for low and high input voltages.


Notice that the threshold voltages are not identical for all the different levels, as well as mobilities, etc., as such, the models are not comparable to – in this case – make a true judgment what’s the most correct model. The same holds for my graphs which have different scales and some with zoom adjusted, etc. Just look for the tendencies.

Different transistors models also try to model different physical phenomena and I will leave it to you to do the research in all books out there.

So, in short – check what you are simulating. Did you switch in correct netlist, correct parameters. Are there discontinuities in the curves? Probably, there shouldn’t be any. Etc.