Upcoming exam, TSEI01 Analog Circuits — Small-signals

Aah, enjoying the Christmas Holidays and New Year and Epiphany. Almost too long vacation this year. A few days from now, there will be another exam in TSEI01, Analog Circuits and I have to compose it.

Students are coming back from hibernation too and their questions start popping up in my email inbox. I Might as well gather some comments here for all to see.

Small-signal schematics

Last year Dr. Thunder (his exam, btw, was auto-generated – more or less – with his cool LaTeX template) composed the exam and one of the questions was this:


Essentially, a single-bipolar gain (?) stage, or at least buffer, with input/output isolated by large capacitors (“stora”).
How to derive the small-signal gain, i.e., the AC gain (at low frequencies) for this stage?

The answer can be quite quickly derived by observing the fact that the input connects to the base (through a large capacitor) and output connects to the emitter (through a large capacitor). We know, for a bipolar, the relationship between base and emitter voltages as VE = VB – UBE, where UBE is more or less constant (assumed to be) 0.7 V.

This means that VE = VB – 0.7, i.e., Uut = Uin – 0.7, give or take, and if we would take the derivative of Uut with respect to Uin (at the operating point) we would get the small-signal gain and since the derivative of the right-hand side of the equation is 1, we can conclude that gain is at least close to unity, i.e., a buffer, a level-shifter.

Doing it the right way?

Anyway, this particular exam exercise will not show up on the next exam (or ?) and the student’s question was instead related to how to analyze/compose the small-signal schematics of this particular exercise.

My suggestion is to do some of the work graphically, in several steps, and sort going easy forward. The suggestion is illustrated by the picture below (click to enlarge). The are more or less the graphical interpretation of your manipulation of the equation systems. It is much easier to debug and back-track if you end up with strange results in your calculations/answers.


The steps

A quick description of the steps:

  1. Start with the original schematic, as a large-signal component. In our case a postive supply (red) and a ground (black).
  2. According to superposition, we should in the small-signal model put all large-signal sources to zero. A DC voltage (source) becomes a short to ground, i.e., setting its value to 0. A DC current (source) becomes an open circuit, i.e., setting its value to 0 (!). The black lines represents signal ground.
  3. Assumption: very large capacitors will become shorts (not the trousers). Redraw schematic accordingly.
  4. Apply your model. There are many different models available and there is not a single “correct” answer. There might however be models that are more applicable than others that makes your calculations simpler. Pick the one you are most comfortable with.
  5. Plug the model into the shematics “as-is”. Don’t complicate by folding and rearranging in advance. From this picture (5) you can sort of cross-check your small-signal schematics with your original schematics.
  6. Now, start folding down everything connected to ground.
  7. Redraw the schematics a bit more conveniently (?). In this case, just a a redrawing.
  8. Redraw the schematics a bit more conveniently (?). In this case, the resistors on the right are coupled in parallel. My tip is to do these steps also graphically since it improves understanding.


Then it is sort of time start to apply the equations to solve the problem. Also here you have to choose the methods that you are most comfortable with. There are plenty of ways to attack the problem. Personally, I think that the Kirchhoff Current Law (KCL) is the savior in all cases. Together with Ohm and KVL, of course.

At the input node:

  • ( 0 – uin ) / R1 + (uout – uin) / Rpi = 0

At the output node:

  • ( uin – uout ) / Rpi + beta ib + (0 – uout) / Rout = 0

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