# A quick glance at the EKV model, part 1

A “problem” when scaling down transistor devices is that the good-old models for transistors tend to become incorrect – and in some cases misleading. The reasons for these are many and not really topic of this post. The remedy is normally to ignore this fact and instead use the old formulas (that in fact are really good for hand calculations) and march on. They will typically give you a result which you can sort of live with. It points out the directions towards the highest gain, or widest bandwidth, or lowest distortion. Then you fine-tune in the simulator anyway.

## The EKV model

The EKV model is suggested as a replacement to the old formulas. That is good, because the EKV model scales comparatively well. However, it is also bad, because it is not really designed for hand-calculations they way we are used to it.

The essence is that you, rather than thinking voltage-in-current-out, or voltage-or-current-in-transconductance-out, you think maximize-the-gm-over-id, sort of. So, it is well-suited for the so-called gm-over-id method.

Let us look at this method… and introduce a few definitions. First, the inversion coefficient:

$IC = \frac{I_D}{2 n \mu_0 C_{ox} U_T^2 (W / L) }$

where $\mu_0$ is the charge mobility, $C_{ox}$ is the gate oxide per unit area, $U_T$ is the good-old $k T / q \sim 26$ mV. W and L are the physical transistor dimensions. Let us use

$S = W/L$

and a normalized gm-over-id as

$\Gamma = \frac{g_m \cdot U_T}{I_D}$

Let us also set

$I_0 = 2 n \mu_0 C_{ox} U_T^2$

such that

$IC = \frac{I_D}{S \cdot I_0}$

and thus, if we like to,

$IC = \frac{g_m \cdot U_T \cdot I_D}{g_m \cdot S \cdot I_0 \cdot U_T } = \frac{g_m \cdot U_T }{ S \cdot I_0 \cdot \Gamma }$

Different sides of the same coin.

We are soon going to plot the Gamma as a function of the inversion coefficient. Let us first understand the formula above. What happens if IC goes towards zero? What does that mean? Well, in the formula, we have three coupled variables: current, width, and length. So, either current or length goes to zero, or width goes to zero (or a combination). As designers, we recognize this behavior from the subthreshold domain. If IC goes to infinity? This means current goes high, S goes low. This is typically our switch behavior, and thus we have for large IC a transistor operating in the linear region. My oh my, what might come in-between? The good-old saturation region, and in fact, designing for IC = 1 centers the transistor in saturation.

## The beauty 1

Now, if we plot the normalized Gamma as a function of the inversion coefficient, we will see that it will more or less look identical for all transistors, independent on minimum length (with same S of course). There will be some minor differences dependent on material, threshold variation, etc., but essentially follows the curve. This is shown below in logarithmic scale. We have set the size aspect ratio to S=1.

It is now up to you as a designer to find the set of curves for your process. Characterize the gm-over-id family of curves and use that graph to look for the maximum gm-over-id.

## The beauty 2

The other beauty is that we do not have to split our mindset into different regions. Instead, we think in terms of gm-over-id and let the IC tune itself – sort of. (Example to come).

Note that the expression contains a large signal component (the drain current) and a small signal component (the transconductance). Also, from “previous” hand calculations we know that e.g. the gain of a transistor is $g_m / \lambda I_D$, i.e., we can from the graph more or less see the intrinsic gain immediately. We also see from this graph that the gain is highest for the subthreshold region. The large-signal parameter we use to control the gm-over-id value.

## Example

Let us find the gain of the transistor setup. A common-source with resistive load, and think a bit differently. First of all, we do not care about the region. We just say that the output voltage should be centered around half the supply voltage. Further on, we assume that the load resistance is much smaller than the transistor output impedance. We can then formulate the transfer characteristics as

$v_{out} = g_m \cdot v_{i n} \cdot R_L$

So, what does that have to do with gm-over-id? Well, not much – however, let us use the fact that we know the output DC voltage.

$A_0 = \frac{v_{out}}{v_{i n}} = \frac{g_m}{I_D} \cdot {I_D \cdot R_L} = \frac{g_m}{I_D} \cdot {V_{D D} / 2} = \frac{g_m \cdot U_T}{I_D} \cdot \frac{V_{D D}} { 2 U_T } = \Gamma(IC) \cdot \frac{V_{D D}} { 2 U_T }$

Here we now see something interesting. We have one component being the gm-over-id component which would depend on our chosen modulation index. The other one being a “constant”, only dependent on the supply voltage and the 26-mV “constant”. An option could now be to look for the highest gain or the lowest distortion, etc. The first term is found from the characterized transistor graph. The other term multiplies the value to give the gain.

Now off to enjoy some more of Africa, and then next part tomorrow, hopefully.