# Early in the morning …

The last few weeks there have been quite a few questions popping up with respect to the Early voltage (or Early effect) for sub-micron CMOS transistors. Why, one could wonder… The Early voltage is perhaps more widely used for BJT transistors and in the CMOS case we use more the terminology output conductance, conductance, and channel length modulation in some form. Therefore, I will use the term Early voltage, VE, a bit sloppy throughout the text.
So basically, this post is just an orientation around a small test bench and some comments. The ambition in the end is a bit larger and requires some more work and I will return to that in a future post.

## Where do we start?

Consider the expression for the drain current in the saturation region:

$I = \alpha \cdot \left( V_{GS} - V_T \right) ^2 \cdot \left( 1 + \lambda V_{DS} \right)$

where we have the channel length modulation effect indicated by the lambda times the drain-source voltage. Lambda would then be somewhat like the inverse Early voltage. Now, the equation above is still an approximation and not really valid for low geometries. There are several of the parameters that need modification to become more accurate.

However, it is not really needed to be too accurate in the hand calculations. If we want a very accurate calculation we have to spend way too much time and often it does not really help us. Instead we rely on the trends (increasing this yields that, decreasing that yields this, etc.). To obtain accurate results we use the simulator.

Assume now we connect our transistor as in the testbench below. The ambition is to measure the current through the drain of the transistor.

If we sweep the drain-source voltage and plot the current, we would get a behavior like the one below

In the picture, we show both the (arguably) “wanted”, blue curve where the current is independent on the drain source voltage in the saturation region (to the right of the dashed line). The red curve indicates a more realistic case where the current in the linear region is not so linear, and where the current in the saturation region is dependent on the drain-source voltage. The latter is undesired, since that would create a transistor with a non-zero output conductance, i.e., the current is dependent on the voltage across the output terminals, i.e., its functionality as a buffer is poor. We can also interpret it in terms of its intrinsic gain.

A comment here is also that the velocity saturation affects the result. We will however not talk about that for the time being. We will also avoid other third-order effects in our argument. We want to originate from the simple first-order function and use that. However, we will do some modifications to the channel-length modulation, i.e., the inverse Early voltage.

Let’s look at the picture again, but now with an extrapolated line from the current to the point when it crosses the x axis.

That crossing point forms the Early voltage. It is from the picture quite obvious that the extrapolation line could be quite sensitive and there could be large variations depending on how we fit that line. For the ideal, wanted, blue case, we see that the early voltage is infinitely large. For low geometries, the Early voltage will approach the y axis rapidly and for say 45-nm processes, the early voltage is at a few volts.

$I = 0 \rightarrow \alpha \cdot \left( V_{GS} - V_T \right) ^2 \cdot \left( 1 + \lambda V_{DS} \right) = 0 \rightarrow \lambda V_{DS} = -1$

## Simulating

Further on, “within” the same process, the drain current varies a lot with transistor width and length, drain and gate voltages. (Some of these variations are of course natural per se, but I refer to the template function as above). With shorter and shorter lengths the template changes. These short channel effects typically make the channel length modulation depend inversely on the channel length and cannot be considered a constant.

$\lambda \sim 1 / L$

In the picture below we have plotted the currents when varying length from 100 to 1000 nm and widths from 0.5 to 10 um. Gate voltage is swept from 0 to 1 V.

To clarify the graphs a bit, we can normalize the current with respect to the width/length ratio. This gives us perhaps a slightly more understandable graph. We see more distinct groups in the family curves, and we can see that for some of the curves, the slopes are quite difference. Compare the center ones with the top ones, for example.

## Where to go from here?

Now, say that we accept that the formula above is just a bit wrong, within the pretty large variations that hand calculations give. Can we make them just slightly more useful/reliable?

First, we can do a derivation of the current with respect to the output voltage (using the equation above), i.e., the first linearized model. From that formula, we can find the lambda and hence also the Early voltage. We get something like

$\lambda = \frac{\frac{dI_D}{dV_{DS}} / I_D }{1 - \frac{dI_D}{dV_{DS}} \cdot V_{DS} / I_D } \rightarrow V_E = \frac{1}{\lambda} = \frac{1 - \frac{dI_D}{V_{DS}} \cdot V_{DS} / I_D }{\frac{dI_D}{V_{DS}} / I_D }$

From the simulated data we have at hand, we can manipulate such that we get a whole lot of family curves describing lambda, in various shapes. By inspecting the curves, we also quite clearly see that the Early voltage increasing with longer channels. In fact, for this particular 65-nm process, it varies between 0.2 (!) and 15 V in this particular process. (From the graph, we also see some “ill-conditioned” cases , i.e. subthreshold. We also see cases where the maximum output conductance yet has not been reached. The relationship between sizes and voltages are also a bit ill-conditioned.)

Compare this to the gain expression of the transistor (assuming small-signal parameters):

$A_0 = \frac{g_m}{g_{ds}} = \frac{ 2 I_D / \left( V_{GS}-V_T \right) }{ \lambda I_D } = \frac{2 V_E}{V_{GS}-V_T } = \frac{2 V_E } { V_{eff}}$

where veff is the effective gate voltage. One would from this formula think that you should be able to crank out a gain of some 2 times 15 over 0.2 V = 150 times, to use the rule of thumb. This is not all true, since the effective gate voltage is quite high for the upper graphs… At least we have ball park numbers now given this simple analysis. If we want to study the formula above a bit more in detail, we end up in the gm-over-id design methodology. That’s probably a topic of another post too.

## Going MATLAB on the curves

Now, the idea is to do some curve fitting… Already now, using a Taylor expansion, we can for example see that there is a square component hiding there. What if we take the whole sha-bang into MATLAB and play around a bit with different models and fit them to curves using the least square methods?

ocnPrint(?numberNotation "scientific" ?output "lambda.txt" ?from 0 ?to 1.2 ?step 0.001 1 / (deriv(i("/Mtrans/d" ?result "dc")) / i("/Mtrans/d" ?result "dc") / (1 - ((deriv(i("/Mtrans/d" ?result "dc")) / i("/Mtrans/d" ?result "dc")) * v("/vDrain" ?result "dc")))))