# Why doesn’t the gain change in my CMOS current-mirror amplifier?

Some weeks ago we discussed why the gain does not change in a CMOS common-source stage. The requirements were perhaps a bit academic: the input and output DC voltages could not change. This implies that the gain is fixed, unless we change the channel length (something that will turn out to be true in this post too…)

## Current-mirror OTA

Another amplifier structure is the current-mirror operational transconductance amplifier (CM-OTA). It consists of an input differential pair with current mirrors copying the differential-pair current to the output branches. The circuit is shown below and is discussed in several text books. Since the circuit is (almost) all symmetrical I have indicated the four most important transistors in the circuit, 1 to 4. Transistor 1 is part of the differential pair, transistor 2 and 3 form a current mirror and transistor 4 is “complementary current source”.

## Analysis

In fact, we see that there are three current mirrors in the circuit. This calls for three different mirror ratios: M, K, and P, in the figure. In a balanced circuit we have to put some relations between these currents. The two currents in the output branch have to be equal at the DC operating point.

 $I_y = K \cdot I_0 / 2$ $I_x = M \cdot I_0 / 2$ $I_z = P \cdot I_x$ $I_z = I_y$

and concludingly

 $K = P \cdot M$.

For example, if K=3, then P and M could be 3 and 1, or preferrably 1 and 3, respectively, to save power and area.

## DC Gain

Let us derive the DC gain. That could be done by looking into the small-signal schematics. This is found in the picture below. We have already made the circuit differential in this case by indicated the input differential voltage, vin, being multiplied by the transconductance of transistor 1. Therefore, arguably a bit incorrectly, the active current source has been omitted in transistor 4 due to that reason.

 $v_x = - \frac{g_{m1} \cdot v_{in} }{g_{m2} + g_2 + g_1 }$ and $v_{out} = - \frac{g_{m3} \cdot v_{in} }{g_4 + g_3 }$

Combining these two gives us

 $v_{out} = - \frac{g_{m3} \cdot g_{m1} \cdot v_{in} }{\left(g_{m2} + g_2 + g_1 \right) \left( g_4 + g_3 \right) }$

From which we can identify the DC gain. The capacitive load is omitted in the equations.

(Due to the pathetic printer policy at our university – in the year of 2014 they still cannot offer us a functional printer system. I remember the days when I had a printer next to my computer and I just pressed “print” and then the paper came out… – I have instead taken a snapshot photo with my shaky phone on this page).

## Approximate

We can now investigate the gain expression from above. First, we can do the “normal” assumption that the transconductance is much larger than the output conductance of the transistor. This is not necessarily the case for modern processes (intrinsic gain in 40 nm is around 5-10) but yet:

 $g_{m2} \sim \frac{ 2 I_0 / 2 }{V_{eff2} }$ and $g_{m3} \sim \frac{ 2 K I_0 / 2 }{V_{eff3} }$

The effective voltages are the same for both transistors, 2 and 3, they share both gate and source voltages and we assume the threshold voltages to be the same. This means that we get

 $g_{m3} = K \cdot g_{m2}$

Let us use that relation in the previous equations and we end up with

 $A_0 = \frac{v_{out}}{v_{in}} = \frac{K \cdot g_{m2} \cdot g_{m3} }{g_{m2} \cdot \left( g_3 + g_4 \right) } = K \cdot \frac{g_{m1}}{g_3+g_4}$

so here one would now think that by increasing the mirroring factor between the two branches, we would then “efficiently” increase the gain of the amplifier. Actually, it is not very efficient, since it just scales linearly from a gain which already is quite poor. It would be nicer with exponential increase…

## But

Notice that there is a hidden relationship between mirror ratio K and the output conductance which is not directly visible in the formula. We know for example that the conductance is linearly dependent with the current (first-order approximation).

 $g_i = \lambda \cdot I_i$

So, from this we deduce that for transistor 3 we must have

 $g_3 = \lambda_3 \cdot I_y = \lambda_3 \cdot K \cdot I_0 / 2$

The same holds for the fourth transistor. Now putting these together:

 $A = \frac{v_{out}}{v_{in}} = K \cdot \frac{g_{m1}}{ \lambda_3 \cdot K \cdot I_0 / 2 + \lambda_4 \cdot K \cdot I_0 / 2} = \frac{g_{m1} / I_0 }{ \left( \lambda_3 + \lambda_4 \right) / 2} = \frac{1 / V_{eff,in}}{ \left( \lambda_3 + \lambda_4 \right) / 2}$

shows that the gain is independent on the mirror ratio… It is the current in the first stage that sets the gain of the amplifier, i.e., it is more or less the same gain as a single common-source stage! Stepping back to that good-old post shows us once again that not much can alter the gain, but changing the input voltage level and increasing the channel length.

Tip: Do the calculations for a cascoded version.

## Why bother with the current-mirror OTA then?

Well, even if the gain is low in your amplifier – using the simple approach as above, it effectively forms a differential-to-single ended conversion which could come handy. Further on, with mirror ratio, you bypass the relationship between slewing and gain as you would see in a single common-source stage. The slew rate is given by $SR = K I_0 / C_L$, but the gain is given by $I_0$ “only”. We can maintain the gain, referring to $I_0$ and increase the ability to drive large capacitive loads.

## Single- or two-stage amplifier?

Given the results above, one can say that in its simplest form it is a single-stage amplifier. However, there is an additional pole introduced at the transistor 2 and 3 gates. One can see the amplifier as a two-stage amplifier with two common-source amplifiers. The first has an active diode load, the other one a constant current source load. Due to the (comparatively) low impedance at the load of the first amplifier and the (comparatively) large load at the second amplifier, the poles are likely to be well separated.

For this reason, one typically wouldn’t size K too big as it would give you a second pole sneaking up on the first pole and destroying phase margin. Play around with the poles and see.