## Background

The other day I provided the students in my course: “TSTE08 Analog and discrete-time integrated circuits” a quiz. Perhaps it was a bit of a cryptical one, but I wanted to point out some of the difficulties with the current-voltage relationship in an analog amplifier, and the complexities in the choice of electrical vs. physical design parameters.

So, with this post I hope to give you both an insight in that quiz, but also an insight in a clever (?) way to set the DC operating points in your circuit…

## The quiz

The quiz related to the common-source amplifier. The input is typically connected to the NMOS and a PMOS forms as active load. Moreover:

Assume I have a common-source amplifier with an active load. Further assume that the output and input DC voltages are fixed.

What should I do to increase the DC gain of my amplifier? Use hand-calculation formulas.1) Increase the current through the amplifier

X) Increase the width of the transistors

2) Increase the length of the transitors

Any combination of those three could be correct.

So, perhaps the quiz it was a bit cryptical, yes.

## Solution

First suggestion on how to attack the problem: find the desired relations you need. For example, the gain, is something like:

where we can clearly see that it is “independent” (!) on the current through the amplifier. The

is the effective input (DC) overdrive voltage (which we cannot touch as per the quiz!). We also know from “hand calculations” that

and since cannot change we also see that obviously has to be constant.

Technically, we could increase both current and size such that the ratio is kept constant. However, it still does not help if we look at the gain expression above. The gain is independent on the ratio, if the effective voltage remains constant.

**Options 1 and X are no valid options.**

So, what about transistor lengths?

Also here we need to look at another common relation for a MOS transistor: we know that with longer widths, the channel length modulation reduces, so we get:

such that

the channel length pops up in the numerator.

*This means answer 2 is correct.*

By increasing the channel length of the transistors, we effectively increase the output impedance and also increase the gain without touching the DC level (hand calculations).

## Is that really correct?

Well, is it really correct? Maybe not super-duper correct if we take all second- and third-order effects into account. There are probably small variations to the gain if we change current and width.

Let us hook up a testbench. Below we find a common-source stage with a somewhat cryptical circuit in the box on the top. That is actually a tuned current source that guarantees that the the operating points, input and output DC voltages, are kept constant. The loop with the vcvs (amplifier) will increase the current through the circuit and make the output voltage follow the reference voltage in the top left. If we also make sure that the transistors are sized well to operate in saturation region for the sweeps we will do shortly, we are more or less fine to prove our point.

Then we run a DC input voltage sweep and an AC input sweep. Below we find the frequency response on the left and the DC response on the right. The left-hand figure tells us that the DC gain is somewhere around 25dB-ish. From the right-hand figure, we see that the output DC voltage stays stuck at some 0.6 V.

### Varying widths (effectively changing current)

We do a parametric sweep and capture the DC gain value (from the frequency sweep at 10 Hz) and plot it as a function of the transistor width. (Sorry for the thin line here, you might have to press the picture for a more clear view.) We see that the gain increases from some 23.5 to some 24.7 dB when increasing the width 100 (!) times. In a linear scale that is a very small change for such a large variation and practically there is no (significant) change in gain.

### Varying lengths

Then we do a parametric sweep and capture the DC gain value, still at 10 Hz from the frequency sweep, and plot it as a function of the transistor length. (Sorry for the thin line here, you might have to press the picture for a more clear view.) The gain now increases 17.5 to 28 dB when increasing channel length 10 (!) times. In a linear scale this is now a very significant change, almost four times (12 dB).

### A comment on the test bench

The trick in the test bench is quite useful actually. It is much more convenient than running the circuit in open loop to try to find the absolute settings. If the gain is very high, you have to do quite a few sweeps around the operating point in order for the simulator to have you find the best point.

The trick is also the convenient `sp2tswitch`

that Cadence/spectre provides to simulate a circuit in different conditions. The AC simulation (which is run after DC) will inherit the DC settings and run the AC analysis around those operating points. Notice that I had to connect the two inputs of the vcvs (essentially an differential operational amplifier with a gain of 1000) to the reference voltage during AC to force the gate of the PMOS to be quiet. It is not clear why this was needed.

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