Ok – so got carried away with the Limerick. (It’s indeed a nice way to be cynical and ironic and make a point – at the same time! )
With some inspiration from my brother-in-arms, Niklas, I came up with this one:
Connecting by naming is kind of nice
Keep in mind to follow this advice
stick to the check list
minimize the risk
Else we invert the 'POWER DOWN' twice!
Almost a true story 😉
So what is it about? Well, it is so annoying to find that designers tend to name the nets and blocks in all possible strange ways, Why not the favourite one:
inv_new or good-old ones like
amplifier_Old even though it is still used in the library.
Further on, we have had cases when people have named the wires/ports/pins:
PD_L. Interpreted as “Power Down – active low”. But no! It is “Power Down – referring to low-voltage domain”. Thank you, FIB! Welcome, re-spin!
Why not simulate to verify? You should, of course, but sometimes time pressure, complexity in running full-chip verification, inadequate models of analog circuits, etc., “forces” you to connect-by-naming on the top-level.