# Top Ten: Circuit Analyses

In this top ten list I go through some typical analysis for analog circuits and try to order them according to complexity, etc.

Once again, I assume fairly trivial analog blocks such as amplifiers, bias circuits, etc. I am excluding more complex blocks like PLL, ADCs, and DACs that are kind of systems of sub-systems. For those guys, the simulation complexity increase more than exponentially… Let’s get back to the latter ones in another list…

So, these bullets are ten out of many, of course. Please add your own tricky analyses if you like.

And further on: optimization on top of all these bullets could be applied. For example, AC frequency response could imply that the DC operating point need to be moved. I have also omitted Monte Carlo analyses, corner analyses, and dynamic drift analyses.

• #10: DC : Finding the operating point

The kind-of-basic of design. The DC operating point of the circuits needs to be found. The first-order approach is quite simple: for the amplifier, find the DC point which gives you highest gain and largest signal range. The largest signal range would traditionally be defined by the region in which all transistors are in saturation region, but should be modified to a measure such as the range in which I obtain a certain linearity.

Remember, though, that there might be several DC operating points! The DC operating point might also shift once you put your circuits in e.g. a feedback configuration or some other kind of loop. Do not forget to run your analysis over all cases and all levels. You are probably also quite likely to have several different modes of operation, for example, power-down, low-power, high-speed, low-speed, etc., for which you will have different operating points.

• #9: AC : Frequency response

The frequency behavior of your component is quite likely dependent on #10. I would probably say that AC analysis is simpler than #10, but I have also reflected the order of analysis by putting AC analysis above DC analysis. However, in the AC analysis we also identify all the poles/zeros in the transfer function of our circuit. This information is later used in #3.

To the AC analysis we should add some more dimensions: power-supply rejection ratio (PSRR), ground rejection raio (GRR), common-mode rejection ratio (CMRR), etc. In quite a few cases there are contradictive results and you need to do those analog trade-offs. In the single-ended common-source amplifier, remember that the ground-rejection ratio is “untouchable” (if NMOS is used as input) and that the power-supply rejection ratio should be optimized by making the PMOS load as weak as possible. I guess it should be noted that these measures make most sense in a differential world. Also, remember that the PSRR and GRR are very sensitive to mismatch! Take the simple example with two identical amplifiers in parallel where the PSRR ideally would be infinite. However, very small mismatch errors would give significant contribution.

Quite often I use the DC+AC analyses in a small optimization loop (by using an ocean script executed by Spectre). I sweep the DC variable, find the A_0 DC gain, the phase margin, etc. This gives me an AC characteristics as a function of the DC variable. I can then characterize the DC range. Further on, by also invoking MATLAB on top of this I can optimize with respect to this curve.

• #8: Transient : Settling/Slew-rate

DC and AC are of course not the only analyses (we have 8 more bullets!). Quite a lot of information is obscured and a transient analysis will help us to understand our circuit most. Measures such as slew rate can only be found by a transient analysis (or possibly steady-state analysis).

There are plenty of more things and there could be quite a few tricky setups in the simulator required to get it going. I have deliberately decoupled this bullet from a few of the others below.

• #7: Startup : Influence of power sequences

I have decoupled #7 and #6 from the transient analysis in #8. The influence of power sequences is most likely verified by a transient simulation. Quite often, the beginner’s mistake is to never touch the supply, but instead assume that the supply-voltage is “always-on”, i.e., fixed by a DC voltage source. However, there are many scenarios: (1) the supply voltage could rapidly ramp-up from 0 to VDD, (2) it could slowly (compared to the time constants in your circuit) increase to VDD, (3) overshoot and ring due to the RLC in bond-wires, decoupling capacitors, etc., (4) spike, i.e., go to VDD, back to ground, and back to VDD. What you want to investigate in these scenarios could be: (a) do I have any short-circuits during these sequences forcing very cross currents from supply to ground, (b) do I have dynamic nodes that latch to undesired levels, (c) metastable phases causing some sequencer to become incorrect, (d) do I have a robust power-on-reset circuit handling all these cases, (e) some bulk configurations causing say latch-up during start-up.

There are other scenarios: you have different power domains and different regulators powering the different domains. What happens if you have different power-up sequences between them? Could it be that you have a short-circuit from one domain to another due to some nodes being improperly defined.

Same kind of arguments could hold for the case of turning the power off.

• #6: Power-down/Dynamic nodes : Are there any floating nodes?

Quite similar to #7, but for power down we are more aiming to turn some reference bias currents down. Are there any dynamically latched signals where the voltage is kept by a capacitor or back-to-back inverter at a certain level? Could this level make some transistors to turn on? Are all the gates tied to ground or VDD during power-down? Add extra pull-down/up switches on undetermined gates such that you do not get a case where the PMOS gates are pulled down to ground and NMOS gates to supply. This could more or less create a short between ground and supply and the aim to reach low power was kind of lost.

Look at a simple differential stage and notice that all levels are not really well defined if you would cut the main bias current!

• #5: Noise : Tackling the noise sources

Noise is worse than you think and for low-geometry processes it becomes even more troublesome: the 1/f noise knee increases with approximately v_eff^2/L. With lower channel length, L, it increases dramatically. Further on, the V_eff tends to become smaller and smaller, due to the lower voltage range and threshold voltages that do not really track the voltage shriking.

For example, you have an amplifier for a 16-bit converter. Your swing is 1-V, you have a bandwidth of half the sample frequency (anti-aliasing). Your quantization noise level is 4.4 uVrms. To not affect this budget, you should (practically) have a factor 10 less noise power. Thus, your amplifier needs to have a noise level of some 1.3 uV. So, is this much? Well, let us start with the input-referred noise of a “modern” MOS: 4 kT gamma / g_m. The kT (Boltzmann constant time the absolute time) is approximately 4e-21 at room temperature. gamma is some 1 to 1.5 nowadays (no more Mr. 2/3-guy). Assume the rather large g_m of 1 mS and that we have a 1-MHz bandwidth. If we crunch the numbers: 4 * 4e-21 * 1.5 / 1e-3 * 1e6 ~ 5 uVrms. Hmmm… and that’s the input-referred noise…

So, in short, do not underestimate the noise and design for it quite early in your flow.

• #4: Periodic steady-state : Modulation

Quite often nowadays there are multiple frequencies involved. Mixers, PLLs, switches, etc. Actually, on the top of this page I promised to not talk too much about “larger” circuits like ADC, etc. However, even smaller circuits may contain some multiple frequencies. Take the sample switch for example. How does the switched output look like? What’s the nonlinearity, etc. For this purpose, the periodic steady-state (PSS) analysis comes handy. The sample switch actually works like a mixer. And, remember that in the front of the ADC, the sample-and-hold might actually be used as a subsampler and not only representing the first Nyquist range at its output. We will get back to this in #3 below.

Anyway, the periodic analysis as such is not that difficult. The problem is to set up all the involved frequencies and correctly identify the bands we want to investigate with the simulator. (If we mix two frequencies, where is the desired band if when using IQ modulation and we only simulate one of the channels?)

It is also rather tricky to backtrack the results to the design parameters. Where are the bad guys in case some of the specification points are not met? I’ll leave that to the RF guys.

• #3: Switched circuits : Transfer characteristics

We talked about the sample-and-hold switch in the previous bullet. The switched-capacitor (SC) or switched-current (SI — it’s coming back!) circuits are in some sense multiplying circuits and the PSS (see #4) could (should) be used to analyze the settled outputs of an SC or SI circuit. The advantage is not only in the time-domain, but actually in the AC or noise domains. Spectre, for example, supports the so called PAC analysis that enables you to do an AC sweep in a switched environment. For SC and SI it is rather straight-forward, you normally only use the baseband (up to half Nyquist theoretically, but practically much lower than that).

So, when you run switched circuits, try the different periodic steady-state analyses. Do not forget to compensate for the sinc-weighting! Notice that the tool still sees a piece-wise linear signal at the output of your SC/SI circuit.

• #2: Stability : When is your circuit stable

All these stability criterion that you hardly know the name of… Maybe this item should be #1, but I left it here as in the “normal” cases — for the simpler circuits we have used in this list — you tend to end up with fairly simple solutions to stabilize your circuit. For analog design, and especially high-speed design, you should be aware of Prof. John Choma once so clearly concluded: “You will always have feedback”. This feedback path can be anywhere: internally, externally, through PCB, through substrate, through parasitics, through some unforeseen path, etc. This is a rather vast field and a top-ten list topic could very well be “top ten: stabilization techniques” – I guess I will come back to that then…

• (1) in low-voltage regime you need multiple stages and quite likely the nested Miller compensation technique to stabilize your circuit,
• (2) don’t use the pole-zero cancellation (nulling) approach in the two-stage amplifier. It is tempting, but dangerous and you want to avoid that doublet if you miss the pole,
• (3) don’t be afraid to verify stability in the time-domain. The transient results contain exactly the same information as the frequency domain does.
• (4) stability could differ quite a lot dependent on operating region, i.e., don’t forget to vary the DC point a bit.

And there are plenty more …

• #1: Switched noise : Is it correct – or not?

Practically, the same type of analyses holds for a switched environment as for a continuous-time environment. Each one of the noise sources will see a certain transfer characteristics to the output. We can then sum up and weight all the spectral densities according to corresponding theory. The tricky part, though, is that it is so tedious in the pen-and-paper format.

Also, what happens if the noise bandwidth is wider than the sample frequency? How much of that noise does really fold into your baseband, everything? (No, not necessarily is the correct answer dependent on the bandwidth of your system).

What happens during various different reset phases? How is this noise stored/accumulated? If the reset pulse occurs rarely, it is not really noise, but merely some kind of offset or 1/f noise during that period.

What about phase jitter from the clock. Is it harmful in a switched-capacitor circuit? (Well, yes it is, but how harmful?)

Further on, in the switched domain filter can become correlated. Take 1/f noise, for example. If we sample really fast, the 1/f noise component found between two different samples will in fact be strongly correlated! Say the 1/f-noise has a 10-kHz knee and we sample at 100 MHz, we will take quite a lot of samples of that “slowly” varying noise). How does this affect the output result? (A way to avoid that question is to use the correlated double sampling technique in switched-capacitor and switched-current circuits to effectively “cancel” 1/f noise.)

So, any comments? Please post your idea of what would be the “correct” list. Hope that some of the open questions I have left stimulates some additional comments.

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