Top Ten:Simple circuit building blocks

It is a sizzling -10 degrees outside and sunny, no wind what so ever, 10cm of snow. Enjoying a cup of coffee and getting some artificial sun tan from my 2 x 24-inch Samsung monitors…

So, this week’s top ten list is a bit related to the courses in analog and discrete-time integrated circuit design (ATIK and ANIK).

I wanted to give my view on the list of complexity of simple building blocks for analog ICs and some tips-and-tricks related to those. The caveat here is that I focus on moderate-speed, moderate-resolution, etc., etc. If we need to go for the extremes, any building block could require immense amount of attention. Another caveat is that I have not done any distinction between cascoded and noncascoded cases. In the first version of the post I will not have any pictures – bare with me – I will update shortly. Also, I hope to paste a couple of formulas too.

  • #10: Resistive divider

    So, let us start off easy. Assume we want to generate a lot of different voltage levels to be used for e.g. biasing or ADC references. We connect a resistor chain of N identical resistors between two voltages (say a reference voltage and ground). Kind of easy … but you need to think about how to decouple those voltages, what kind of current you need to drive through them, noise and matching requirements. Quite often the reference levels are connected to a switched node and there will be a transient on the reference ladder. You can for example trade current through the ladder against decoupling size. Don’t forget to do a proper analysis of the mismatch also! The resistive ladder is most sensitive with respect to most performance measure at the center.

  • #9: CMOS inverter

    The schoolbook example. The first circuit you tend to draw in the courses introducing students to CMOS design is a CMOS inverter. Once again, for moderate speeds it is kind of easy to design. Given a certain load capacitance you design the circuit to meet certain rise/fall/delay times. Quite often (not always!) you design for a symmetrical trip point which tend to give the infamous 1-to-3 ratio between NMOS and PMOS aspect ratios.

  • #8: Transmission gate

    Well, using the transistors as analog switches is quite common in a switch environment and if we want to go for high-speed, high-accuracy, etc., etc., the design can become super-duper complex with boot strapping, clock-feedthrough compensation, charge-injection compensation, etc. In its “simplest” form, it is about matching the NMOS and PMOS on-resistances to achieve the most constant RC time constant for a certain signal frequency band as well as voltage interval.

  • #7: Common-drain

    Common-drain is the amplifier where the driving transistor has its drain connected to a common node (ground or virtual ground) in its equivalent small signal schematics. The common-drain amplifier is a level-shifter or a source-follower. The output voltage is approximately a threshold down (NMOS) or a threshold up (PMOS). Ideally, the DC gain is unity, but a common “mistake” is to assume that this can be obtained in reality. With modern core transistors, a unity-gain is quite hard to obtain due to bulk-effects and due to the fairly low gain of a core transistor.

  • #6: Common-source

    Common-source is the amplifier where the driving transistor has its source connected to a common node (ground or virtual ground) in its equivalent small signal schematics. The common-source amplifier is more or less same as the CMOS inverter above, but the tricky part is to align the active load with the input driving transistor. A common “mistake” is to assume that the gain is very high. With modern core transistors, the gain is limited to say 20~dB or so (give or take some dBs). In its stand-alone form one should notice that the gain is inversely dependent on the input DC level (do the maths!). To get higher gain, we need to lower the input DC voltage and thus also limit the input swing. A lower input V_eff would also make the circuit a bit more sensitive to mismatch but would give us higher swing. Don’t forget to trade off the noise from the active load against output swing! Making the active load transistor too large will increase output noise.

  • #5: Common-gate

    Common-gate is the amplifier where the driving transistor has its gate connected to a common node (ground or virtual ground) in its equivalent small signal schematics. The common-gate amplifier is more or less same as the common-drain, but with a positive gain. The bulk effect (if input transistor is NMOS) will be visible. The tricky part is to align the bias voltage of the input transistor. A common “mistake” is to think that the input resistance is very low, in fact, the input resistance of can be quite substantial … Anyway, since it is not infinite, we say it is “low”, at least it can accept some current.

  • #4: Folded-cascode

    The folded cascode building block is used to “fold” the DC voltage down. The cascoded gain stages tend to make it difficult (if possible) to have similar input and output swings. The folded cascode fixes this issue. Notice though that the folded cascode is actually a common-source stage cascaded with a common-gate stage. It kind of a of two-stage amplifier. Using this approach, it becomes a bit simpler to design. (Speaking of this, notice that the cascoded common-source is actually also a common-source connceted to a common-gate stage! In the former case, we have an NMOS input connected to PMOS, in the latter an NMOS input connected to NMOS input)

  • #3: Current-mirror

    Hmmm, maybe this should end up a bit further down the list, but I put it here anyway so that it comes hand-in-hand with #2. The current mirror is of course a vital building block. In CMOS design you should preferrably bias your “voltage-mode” circuits with currents, since quite often the specifications are given by currents rather than voltages (!) For example: power dissipation, slew rate, bandwidth (gm ~ I). It is simpler to also distribute currents rather than voltages across chips. The problematic issues with the current mirrors (if they are used for biasing) is that they cannot be too big in terms of noise and matching. But if we make them too small, they will limit the swing. (Well, analog design is never kind to us.)

  • #2: Wide-swing current-mirror

    Ok, so I have put this on the second place because of its annoying biasing scheme – especially its sensitivity over corners. The wideswing mirror offers the same output impedance as the cascoded current mirror (#3), but due to its biasing scheme we can increase the swing at its output with a threshold voltage. There are two biasing schemes: either use three transistors on the primary side and two reference currents or use one reference current and set the voltage difference between the transistors with a resistance. The latter is a bit noisy, but simple and less power hungry. For the former, my tip is to create a cascoded unit current source and for the bias transistor you connect several of these in series. (Stay tuned for a picture!).

  • #1: Differential pair

    In retroperspective, one could argue about putting the differential pair on the top of the list. But I wanted to limit myself to building blocks and with the differential pair a lot of additional questions arise: common-mode supression, differential circuits, rejection, etc. It is the “gateway” to the macroblocks (op-amps, comparators, etc., etc. which will be the topic of another list). Also, there are some fun maths around the simple transistor pair (quite similar to those old school book examples for the bipolar differential pair and the bipolar long tail pair. Analyzing the differential pair with respect to mismatch, offset voltage, range, gain, etc., is perhaps not tedious, but it has the potential of becoming a few pages after all.

So, any comments? Please post your idea of what would be the “correct” list.

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