Regarding cadence again. I want to recommend you to use something referred to as pPar in your designs. This is a way to tell cadence to pick up variables defined higher up in hierarchy in the schematic . The use of the parameter is similar to that of the ahdl and veriloga code that you used in the lab.
Search for pPar in the on-line help or in the built-in documentation.
Notice that you sometimes need to update the symbol to get cadence to understand some of the changes you’ve done. Do this update by adding a dummy pin which you later remove.