TSTE16: Using pPar in your design

Regarding cadence again. I want to recommend you to use something referred to as pPar in your designs. This is a way to tell cadence to pick up variables defined higher up in hierarchy in the schematic . The use of the parameter is similar to that of the ahdl and veriloga code that you used in the lab.

Search for pPar in the on-line help or in the built-in documentation.

Notice that you sometimes need to update the symbol to get cadence to understand some of the changes you’ve done. Do this update by adding a dummy pin which you later remove.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s

This site uses Akismet to reduce spam. Learn how your comment data is processed.